In an analog to digital converter or a phase-locked loop, one channel of high-speed clock usually needs to be distributed into multiple channels of low-speed parallel clocks. In addition, for these parallel clocks, a relatively precise phase relationship between neighboring clocks needs to be ensured. Otherwise, for a time-interleaved analog to digital converter, when phases between neighboring clocks do not match, a high-frequency input signal may bring clock and signal related harmonics to a frequency spectrum, thereby affecting conversion precision. Precision or a speed of a conventional time-interleaved analog to digital converter usually cannot reach a certain degree. Therefore, a phase matching problem of parallel clocks is not manifest. As the speed and the precision continuously improve, the phase matching problem of parallel clocks becomes severer.
A conventional multi-channel clock distribution circuit is usually implemented by connecting D flip-flops in series. Each channel of clock passes through different D flip-flops and output drives. Therefore, a clock phase mismatch between different channels generally reaches a picosecond level. A main reason why the relatively large mismatch is caused is that the clock passes through a logic gate. An output transition point of the logic gate is directly determined by threshold voltages of a P-channel Metal-Oxide Semiconductor (PMOS) transistor and an N-channel Metal-Oxide Semiconductor (NMOS) transistor. A mismatch between threshold voltages directly causes a relatively large clock phase deviation between different channels. Therefore, a phase matching degree between channels of clocks is relatively low.